Design reflection for optimal test-chip implementation

A new type of logic characterization vehicle (LCV) that optimizes design, test, and diagnosis for yield learning has been recently described and is called the Carnegie-Mellon Logic Characterization Vehicle (CM-LCV). The CM-LCV is a product-like test chip that uses constant-testability theory and regularity to create a parameterized design that targets the physical characteristics of a product design or family of designs. The logic function of the CM-LCV is, by construction, designed to exhibit near-optimal test and diagnosis characteristics. The physical characteristics however should reflect those found in actual customer designs. In this work, we describe a unique and straight-forward methodology for measuring the physical characteristics of a design and more importantly how to impose or reflect those same characteristics into a CM-LCV. Experiments using both benchmark and industrial designs demonstrate the efficacy of this approach. Specifically, we develop a flow using available tools that can automatically synthesize a scalable CM-LCV in very little time with standard-cell characteristics that are nearly identical to product designs. For example, in the best case, we demonstrate the complete design of a scalable CM-LCV that matches the standard-cell usage of a family of benchmark designs with less than 0.25% error in about 2 hours of compute time.