A 17 GHz programmable frequency divider for space applications in a 130 nm SiGe BiCMOS technology

A programmable frequency divider for fractional-N frequency synthesizers is presented. The input frequency range is from DC to 17GHz for divider ratios from 16 to 255. We show by analysis and time-domain simulations that the quantization noise folding in a fractional-N PLL can be reduced tremendously, if a prescaler between VCO and programmable divider can be avoided by using this high-speed divider. The programmable divider was manufactured in a 130nm SiGe BiCMOS technology. Robust operation is obtained from a supply voltage VCC=3D2.3-3.9 V. The measured divider phase noise floor for a 100 MHz output signal is as low as -156dBc/Hz. The chip occupies 1.7 mm
²
including bondpads and draws 154mA from a 2.3V supply.