I. Introduction
System-on-Chips (SoCs) are getting more and more complex as the feature size of the building transistors scales down. More IP cores can fit on the same die which causes an exponential increase in the interconnection complexity [1]. The performance of individual IP cores used in SoCs is typically optimized by the vendor leaving the task of implementing the on-chip interconnection architecture to the system designer. The task of implementing on-chip interconnects is not trivial since the wiring density directly impacts the system's performance, resources, and power consumption. In some applications, on-chip interconnects can be the system's performance bottleneck which necessitates optimizing the interconnect logical topology. Buses and Networks-on-Chips (NoCs) are the most deployed topologies for on-chip interconnect in SoCs [2].