Generic Self Repair Architecture with Multiple Fault Handling Capability

Built-in self-repair (BISR) approach utilized mostly in regular structures of memory cores has been a promising approach to increase the reliability of any type of integrated circuit. BISR considers spare blocks which in the case of a fault occurrence are used to replace defected circuit parts. A new fault detection and repair procedure with a generic BISR architecture for logic cores is presented in this paper. The architecture is able to localize and repair multiple faults (both permanent and transient), to identify faulty functional blocks, to detect faulty backup blocks, and to repair the core function by employing backup blocks if possible. The number of repairable faults is determined by the number of reconfigurable logic blocks (RLBs) in the core. The whole repair procedure needs only 4 test runs. Experimental results show an additional area of approximately 140% which is still within acceptable level compared to other redundant methods (TMR overhead is 200% without the voter area).