A Low-Overhead Integrated Aging and SEU Sensor

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about 2.7× of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging sensors. Furthermore, the presented sensor can detect and correct half of the single event upsets (SEUs), which lead to a bit-flip in the flip-flop. In addition, by utilizing the SEU detection circuitry, a scheme for reducing bias temperature instability, the most important aging process in the memory structures, is presented by balancing the duty cycle of the flip-flop transistors with negligible extra overhead.