Impact of Interface Layer on Device Characteristics of Si:HfO2-Based FeFET’s

The impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperatures, a ferroelectric field effect transistor with a metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e., ΔtV
_t
> 0), whereas at room temperature, negative threshold voltage shifts (ΔV
_t
) are observed. We demonstrate the relationship between the interface layer and the subsequently deposited ferroelectric layers' effective permittivity: higher permittivity, consistent with a higher tetragonal phase/lower orthorhombic phase content, is noted when the ferroelectric layer is deposited on hydrogen-terminated silicon. In contrast, an anomalous BTI, consistent with a higher orthorhombic phase content, is observed at lower temperatures when the ferroelectric layer is deposited on oxygen-rich surfaces (SiO
₂
, SiON).