Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses (
${t} _{\mathrm{ TiN}}$
). The impacts of
${t} _{\mathrm{ TiN}}$
scaling on the threshold voltage shift (
${\Delta }\text{V}_{\mathrm{ T}}$
), pre-existing hole traps (
${\Delta }\text{V}_{\mathrm{ HT}}$
), generated traps (GTs), and their relative contributions are studied. The time exponents of
${\Delta }\text{V}_{\mathrm{ T}}$
and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with
${t} _{T}{}_{iN}$
. When
${t} _{\mathrm{ TiN}}$
is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both
${\Delta }\text{V}_{\mathrm{ HT}}$
and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an
${f}$
-dependent process and that its relative contribution to
${\Delta }\text{V}_{\mathrm{ T}}$
increases with
${t} _{\mathrm{ TiN}}$
, which is an important factor for the improvement of NBTI through
${t} _{\mathrm{ TiN}}$
scaling.