A +3.0-dBm 115–129-GHz CMOS Power-Efficient Injection-Locked Frequency Tripler Chain

A CMOS power-efficient injection-locked (IL) frequency multiplier chain is presented in this letter. An input IL oscillator buffer, frequency tripler, and IL oscillator buffer were cascaded and designed under an optimum
$V_{\mathrm {DD}}$
to achieve a high-power efficiency. The switched transformer presented both efficient power transfer and frequency tuning. The proposed tripler chain achieved a peak power efficiency of 3.70%, with a 3.0-dBm peak output power at 121 GHz in a 40-nm GP CMOS process. A 115–129-GHz 3-dB output bandwidth was measured under an input power of 0 dBm. The fundamental and second harmonic suppressions were greater than 30.8 and 20 dB, respectively, across the 3-dB output bandwidth. The total dc power dissipation was 53.2 mW under a supply of 0.7 V.