A 25-GHz Power Amplifier Using Three-Stage Antiphase Linearization in Bulk 65-nm CMOS Technology

This letter presents a 25-GHz power amplifier (PA) in bulk 65-nm CMOS technology. To ensure improved efficiency, the proposed PA was implemented using a three-stage antiphase linearization technique. The circuit of the three-stage antiphase linearization technique consisted of the predistortion drive stage, interstage, and the power stage. The positive-signed third-order intermodulation distortion (IMD3) is produced in the predistortion drive stage with subthreshold bias condition and is compensated with the negative-signed IMD3 divided by the interstage and power stage. Consequently, as the class burden of the power stage is reduced, the overall efficiency can be increased. The proposed CMOS PA was operated within a frequency range of 24-27 GHz. For a supply voltage of 1 V, the proposed PA achieved an average output power of 10.3 dBm, power-added efficiency (PAE) of 6.8%, and error vector magnitude (EVM) of 5.17% at 25 GHz for a 20-MHz bandwidth, 64 QAM, and 10.55-dB peak to average power ratio (PAPR) Long Term Evolution (LTE) signal. The proposed PA achieved a 32-dB peak gain, 33% peak PAE, 17.7-dBm saturated output power ($P_{\text {sat}}$ ), and 16.3-dBm output 1-dB compression point.