A $f_{\mathrm{REF}}/5$ Bandwidth Type-II Charge-Pump Phase-Locked Loop With Dual-Edge Phase Comparison and Sampling Loop Filter

The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to $f_{\mathrm {REF}}$ /5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than −121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than −58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm² silicon area.

I. Introduction

For better suppression of phase noise of voltage-controlled oscillator (VCO), the bandwidth (BW) of phase-locked loop (PLL) is desired as wide as possible. However, the BW of PLL is usually designed to be much smaller than its reference clock frequency to ensure stability and avoid unacceptably large reference spur [1]–[5]. In [1] and [2], a type-I PLL shows ~/2 BW while avoiding large reference spur by employing sampling loop filter (SLF). The type-I architecture, however, necessitates additional frequency acquisition circuit. In [3], a type-II PLL is allowed to have BW larger than /10 by employing SLF to isolate the instants when phase error is detected from the instants and the VCO frequency is updated. Because the frequency of phase error sampling and correction is still the same as that of the reference clock, there exists a limitation in increasing the BW of PLL.