A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS

A time-interleaved duobinary transmitter featuring four-way data retiming and a simplified latch + D flip-flop topology to improve the power efficiency and opening of the data eye is reported. A modified bridged shunt-peaking load using a grounded active inductor is also introduced to enhance the operational speed area efficiently. Finally, the two multiplexers, serving directly as the output driver, are summed in the current domain to avoid an extra adder. The prototype exhibits a figure-of-merit of 1.44 mW/Gb/s at 27 Gb/s, and the die area is merely 0.027 mm
²
in 65-nm CMOS.