Adaptively Biased 60-GHz Doherty Power Amplifier in 65-nm CMOS

A 60-GHz Doherty power amplifier (PA) implemented in 65-nm bulk CMOS process is proposed. A novel adaptive biasing network is devised to dynamically adjust the bias voltage of the peaking PA, counteracting its low transconductance caused by the class-C biasing condition. At 60 GHz, the fabricated Doherty PA achieves 22% drain efficiency with a saturation power of 13.2 dBm. The measured results show that over 17% and 8% efficiencies at peak and 6-dB back-off power regions are achieved, respectively, from 57 to 64 GHz.