A Wide Tunable Hysteresis CML Delay Cell for High Frequency

In this letter, a novel high-speed widely tunable voltage-controlled current mode logic (CML) delay cell is implemented in a 65-nm CMOS technology. Variation in the delay of the proposed delay cell is based on the hysteresis control of the output switching threshold by altering the tail current of the CML buffer. The simulation for a single stage cell shows a delay variation of at least 11% in the input clock period at 12.5-GHz clock frequency. While in measurement, the delay line with three stages of the proposed cells shows more than a 38-ps delay variation with an output rms jitter of 1.67 ps for the 9.82-GHz input clock frequency. At this frequency with the highest delay variation, along with additional buffers and delay controllers, the delay line consumes 7.6 mW of power with 1.2-V core supply. The delay line consumes the silicon area of 0.0285 mm
²
in the 65-nm technology node.