I. Introduction
As the abstraction of a system-wide phase-accurate synchronous clock faces its limits in today's complex systems-on-chip, GALS (globally asynchronous locally synchronous) architectures [1] have become the de-facto standard. Here a reliable and efficient data transfer between the individual clock domains is crucial. Among the available solutions, pausible clocking has attracted much interest [2], [3], [4], [5], [6], [7], [8], as it allows an efficient data transfer that is completely free from metastable upsets. This is not only conceptually appealing, it also saves the need for (multi-stage) synchronizers that cause performance penalties in other approaches. Virtually all present implementations of a pausible clock are based on a ring oscillator, whose frequency can neither be accurately designed (only calibrated), nor is it stable, as it is determined by circuit delays which get more uncertain with every new technology node. This calls for a solution that is based on a stable and accurate crystal clock source. However, as shown in [9] gating a crystal clock incurs the same metastability issues as a synchronizer-based data transfer and thus spoils the key advantage of using a pausible clocking scheme.