A new linear delay element with self calibration

Linearity in Delay Element is an important factor in many applications such as Fully Digital Analog to Digital Converters, Delay-Locked-Loops and Voltage Controlled Oscillators. In this work, a new Delay Element is proposed in which the relationship between the input analog voltage and the delay between its input pulse and output pulse is highly linear within an analog voltage range of 0.9V and a delay range of 0.5ns-4.5ns. The proposed Delay Element has been simulated using H-spice with a supply voltage of 1.8V in the 0.18 um CMOS technology. A calibration mechanism based on feedback technique is also proposed which can be used to reduce the impact of PVT variations.