IC design challenges and opportunities for advanced process technology

Moore's Law has entered a new frontier as the incessant progress of device scaling continues to excel in 10nm and beyond. As the physical dimension of devices and interconnect are being shrunk, the design rules and the design flow, for both ASIC and custom designs, face unprecedented complexity. Hence, common IC design practice can no longer separate the design and the process fabrication indifferently. Conventional design optimization techniques also need to take the novel process technologies, such as multi-gate devices (e.g., FinFET), spacer technology, and self-aligned multiple patterning lithography, into account in order to achieve the best possible performance, power, and area for a design. In this talk, the challenges and implication of these new process technologies to IC designers will be touched upon from the foundry's perspective to show how and what to innovate in EDA tools for bridging the gap between physical design and foundry fabrication, and then finally improve the overall design quality and productivity.