Brill tagging on the Micron Automata Processor

Semantic analysis often uses a pipeline of Natural Language Processing (NLP) tools such as part-of-speech (POS) tagging. Brill tagging is a classic rule-based algorithm for POS tagging within NLP. However, implementation of the tagger is inherently slow on conventional Von Neumann architectures. In this paper, we accelerate the second stage of Brill tagging on the Micron Automata Processor, a new computing architecture that can perform massive pattern matching in parallel. The designed structure is tested with a subset of the Brown Corpus using 218 contextual rules. The results show a 38X speed-up for the second stage tagger implemented on a single AP chip, compared to a single thread implementation on CPU. This speed-up is linear with the number of rules, thus making large and/or complex rule sets computationally practical. This paper introduces the use of this new accelerator for computational linguistic tasks, particularly those that involve rule-based or pattern-matching approaches.