Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

We report a record low contact resistivity of sub-1.0×10^-8 Ω.cm² realized on n⁺ In_0.53Ga_0.47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).

Introduction

Recent advances in III-V device technology [1] – [2] have led to an increasing interest in III-V as a replacement for Si in CMOS. To enable this transition, it is critical that III-V process technologies are developed in parallel with progress in device technology. Furthermore, it is well documented that with channel resistance scaling, series resistance becomes a limiting factor in [3].