Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints

As Integrated Circuits (ICs) become more complex through smaller semiconductor feature sizes and higher performance requirements, the thorough testing of silicon devices is becoming a greater economic challenge. System-on-Chip (SoC) test schedules not only need to achieve the shortest possible test application time, they must also satisfy new design constraints which are increasing test scheduling complexity, such as device power. Although many past studies of SoC test scheduling have addressed individual issues during test, none have present a model of test scheduling that has allowed for many different constraints to be enforced at once. By presenting a test scheduling formulation that allows the enforcement of many separate power and hardware constraints, including issues of test pins, as well as allowing the use of modern Dynamic Voltage and Frequency Scaling (DVFS) hardware to further compact test schedules, this study provides a generalized test scheduling formulation that will not only allow the enforcement of multiple testing constraints but will also allow for the further compaction of test schedules and reduction of test cost.