I. Introduction
The demand for increased integration and miniaturization drive modern mixed signal SoCs to contain deeper as well as increased levels of analog-digital interaction. Further, digitally assisted analog circuits, more popular as “algorithmic designs”, have evolved and gained dominance in modern designs due to their several advantages and improved tunability. An example in this context can be given of the capacitive buck converter [1]. Here, a digitally driven capacitive rearrangement assists the converter to achieve the required voltage ratio. Given such a system, it becomes important to ensure that digital and analog coupling are verified since neither have a utility without the other. Owing to limitations with factors such as simulation speed in traditional methods like co-simulations, it becomes difficult to exhaustively verify the system. This hence gives space for bugs in the design.