Chaotic encoder-decoder on FPGA for crypto system

An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2's complement number in digital filter causes the phenomenon called "Chaos" in digital filter. An 1ER filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can be compared to the secret key in private-key crypto system. However, if filter coefficients of chaotic decoder are not same as filter coefficients of chaotic encoder, ciphertext cannot decrypt to get original plaintext. Both chaotic encoder and decoder will be implemented on FPGA to demonstrate the hardware prototype of chaotic crypto system.