A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications

With complementary metal oxide semiconductor (CMOS) technology scaling down, radiation induced multiple-node upsets (MNUs) that include double-node-upsets and triple-node upsets (TNUs) are becoming more and more an issue in storage cells used for applications constrained by their environment, such as aerospace applications confronted to radiations. This article presents a novel triple-modular redundancy without voter based high-impedance state (HIS) insensitive and MNU-tolerant latch design, namely TMHIMNT, to ensure both high reliability and low cost. The TMHIMNT latch mainly comprises triple clock-gating (CG) based dual-interlocked-storage-cells (DICEs) and four inverters. Through three internal inverters, the values stored in DICEs converge to a common node feeding an output-level inverter, enabling the TMHIMNT latch to tolerate any possible MNU. Simulation results demonstrate the MNU tolerance of the proposed TMHIMNT latch. Due to the disuse of C-elements, the proposed TMHIMNT latch is insensitive to the HIS, making the latch more reliable for aerospace applications. Moreover, compared with the state-of-the-art TNU hardened latch, due to the use of a high-speed path, CG technologies, and fewer transistors, the proposed TMHIMNT latch can achieve 98% delay, 17% power, and 29% area reductions, respectively.