Full-custom design and characterization of a phase locked loop — DLS565 using 0.5um CMOS technology

The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were measured and compared to the commercially available LM565C and NE565. It operates with a supply voltage of ±2.5 V with a maximum power dissipation of approximately 22 mW. DLS565 was able to capture frequencies as low as 15Hz and as high as 1.12MHz.