A low power Schmitt Trigger design using SBT technique in 180nm CMOS technology

This paper presents the effect of source voltage and load capacitance on the performance of CMOS Schmitt Trigger circuit with self-bias transistor (SBT) technique which was used to reduce power. The CMOS Schmitt Trigger circuit was modified by designing the transistors aspect ratio on the basis of conventional CMOS Schmitt Trigger and it is implemented using CADENCE Virtuoso in Spectra Simulator using UMC-180nm technology for different modified design. Results are compared in terms of propagation delay, power, and energy-delay product. From the simulation results, the modified CMOS Schmitt Trigger was able to operate between 0.8V to 1.5V voltage range.