Self similarity and interval arithmetic based leakage optimization in RTL datapaths

Low leakage input vector determination in data path intensive circuits is often not feasible through exhaustive simulation. Hence, top down interval propagation technique for low leakage vector determination is proposed in this paper. This technique is a variation to the heuristic used in [1]. For each RTL module, several low leakage intervals are identified. As the module size increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to search the entire input space uniformly to obtain as many low leakage intervals as possible. Based on empirical observations, we observed self similarity in the leakage distribution of adder/multiplier modules when input space is partitioned into smaller cells. This property enables uniform search of low leakage vectors in the entire input space. Also, time taken for characterization increases linearly with the module size. Hence, this technique is scalable to higher bit width modules with acceptable characterization time. We propose a self similarity based Monte Carlo simulation for optimum low leakage interval characterization of RTL modules. The interval propagation is then implemented with the low leakage intervals obtained in the characterization. This yields a reduced low leakage interval set at the primary inputs. The reduced set of intervals is further processed with simulated annealing to arrive at the best low leakage vector at the primary inputs. By applying this low leakage vector, the entire circuit is put in low leakage state. Experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.6% with no area overhead.