Buffer reduction algorithm for mesh-based clock distribution

In deep sub-micron technology, Mesh-based clock distribution is becoming a preferred method to distribute the clock since it is tolerant to process variations. Buffers are placed on the mesh nodes to drive the mesh wire capacitance and large load capacitance of clock sinks. In this short paper, we propose a buffer reduction algorithm which can reduce the power dissipated in clock meshes. We calculate the importance of each buffer by the impact its removal has on the clock latency and clock slew at sinks. We then calculate a rank for each buffer and buffers with lower ranks are removed. Our buffer reduction algorithm is able to achieve 15–18% reduction in power at the cost of 10–20 ps increase in skew when compared to the previously published work.

I. Introduction

Tree-based clock distribution has been the method implemented traditionally in most of the sequential VLSI circuits. However, when tree-based clock distribution is implemented in Deep Sub Micron (DSM) technology, it introduces additional clock skew due to process variations. On the other hand, Mesh-based distribution is tolerant towards variations due to the redundant paths in the clock mesh. But this comes at the cost of increased power dissipation since mesh has increased wire capacitance [1]. A hybrid clock distribution scheme where the leaf level mesh is fed by a top level clock tree is termed tree driven mesh. A detailed study has been made on leaf level clock mesh synthesis in [1], [2] and [3]. Buffers are placed at the mesh nodes (Fig. 1) to drive the load capacitance which is the capacitance of clock sinks (input capacitance of flip flops/registers) and capacitance of mesh wire.