Optimal Redundancy Designs for CNFET-Based Circuits

Substantial imperfections in carbon nanotube (CNT) field-effect transistors (CNFETs) are one key obstacle to the demonstration of large-scale CNFET circuits. In this paper, we first categorize transistors based on the impact of resizing on yield improvement and delay penalty for logic circuits. Then we propose an approach to size transistors in different categories by using redundant CNTs to improve yield/area with user-specified limit on delay penalty. We then propose a hybrid redundancy approach for memory arrays by optimally combining redundant CNTs approach with the traditional spare columns (rows) approach. Experimental results show that the proposed approach provides significant improvements in yield/area for logic circuits at very low increase in delays. For SRAM, spare columns (rows) approach becomes ineffective when it is applied alone since spare columns (rows) themselves have very low yield. The proposed hybrid approach for memory array provides 18% improvement in yield/area compared to a redundant-CNTs-only approach as well as reduces delay penalty on address decoder from 19.2% to 15.7%.