Design and implementation of SPI bus protocol with Built-in-self-test capability over FPGA

The Serial-Peripheral Interface (SPI) protocol is one of the important bus protocols for connecting with peripheral devices form microprocessor. The complexity of the circuits has aroused with the enormous advancement of IC technology. So, in order to lessen the product failure self-testability in hardware is demanded a lot in recent times. The necessity of self-testability will lead to a solution called Built-in-self-test (BIST). BIST is an effective solution to reduce the huge circuit testing cost. This paper represents designing and implementation of SPI protocol with BIST capability over FPGA. The need of programming for setting up a network with two devices is no longer needed in this proposed system. To accomplish compact, stable and reliable data transmission, the SPI is designed with Verilog HDL language and synthesized on Spartan 2 FPGA. An EEPROM and FPGA Spartan 2 are used for the communication testing where the FPGA is master and EEPROM is a Slave.