A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer

This paper presents a 3
^rd
order single loop continuous-time sigma-delta modulator (CTSDM) based on a 4-bit 2b/cycle SAR quantizer which reduces power consumption and chip area. The proposed high speed 2b/cycle SAR quantizer employs switchback capacitor switching procedure to obtain a more power efficient quantizer and a smaller variation of common-mode voltage which alleviates the effect of dynamic offset and parasitic capacitor of comparators. The modulator, running at 200 MHz, uses 0.13-μm CMOS process and achieves 71.6 dB peak SNDR, 71.2 dB DR and 82.7 dB peak SFDR with 5 MHz bandwidth. The power of quantizer is 782 μW.