Low flicker noise high linearity direct conversion mixer for K-band applications in a 90 nm CMOS technology

A design of a Direct down-conversion mixer is presented. Noise performance and power consumption are the target design issues for this work. The mixer is fabricated in a 90 nm CMOS technology; it converts down a 2 GHz channel bandwidth at around 20 GHz to the neighborhood of zero frequency. New current bleeding network with resonating inductors is presented; it provides most of the DC current to the driver transistors, yet highest possible ohmic path for the ac current to ground. Buffer is designed to isolate the high impedance of the mixer output from the 50 Ω load. Noise figure of the mixer along with the buffer is shown to be 12 dB with a conversion gain of 4 dB and compression point of −12 dBm. The mixer core consumes 4.3 mW of power, while the differential buffer has a power consumption of 6 mW. The total chip size including pads is 0.44×0.72 mm
²
.