Motion compensation architecture for 8K UHDTV HEVC decoder

This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.

1. Introduction

Ultra High Definition Television (UHDTV) has been popularized in the recent period. by supporting up to 4K or 8K high resolution, UHDTV can provide better visual experience compared to previous Full HD specification. However, higher resolution means to higher data throughput requirement, which leads to several challenges on real-time design. Firstly, massive data volume means that increasing bit rate is required to compress the huge video content. In order to deal with compression problem, new High Efficiency Video Coding has been standardized by JCT-VC in January 2013. As the successor to H.264, HEVC can achieve 50% video compression ratio while guarantee the equivalent compression quality [1]. Secondly, UHDTV increases the design complexity as more hardware resources are needed to ensure higher throughput. Meanwhile, HEVC also adds extra burden on complexity for hardware implementation because of new coding tools introduced for better compression performance, such as flexible hierarchy structure for coding unit (CU) and so on [2]. Thirdly, memory traffic problem becomes more serious for UHDTV. The demand for off-chip memory bandwidth is proportionally increased to the video pixel rate. Bandwidth requirement may exceed more than 10GB/s for UHDTV. In total, new VLSI hardware architecture is required for HEVC-based UHDTV decoder.