DC blocking capacitor design and optimization for high speed signalling

A full wave modelling approach based on authors' previous work is improved to model DC blocking capacitor. By correlating to the measurement data, it is shown that the modelling approach is accurate. A methodology of developing equivalent capacitor model for signal integrity simulation is proposed to improve simulation efficiency. In order to mitigate the impact from DC blocking capacitor, voiding is studied to find optimal voiding scheme. Full link PCIE Gen 3 simulations is performed as an example to demonstrate design optimization for AC coupling high-speed links and some rules of thumb are derived based on the study.