New circuit model for investigating plasma damage in FDSOI devices

In this work we propose a circuit model to investigate the plasma induced damage on the FDSOI technology. The charging damages are simulated on nMOS and pMOS devices as a function of the plasma parameters and antenna characteristics. We demonstrate that model simulations reproduce the electrical measurements and the FDSOI device behavior for each test structures where different configuration of diode protection and several gate oxide thicknesses are proposed.