I. Introduction
In a single carrier coherent optical transceiver, the transmitter path employs four DACs to generate two complex signals on both X-and Y-polarizations, respectively [1]. To achieve transmitter data rates up to 100 Gb/s and above, high speed DACs with a conversion rate of more than 25 GS/s and with a nominal resolution of more than 6 bit are necessary. A 6-bit DAC with a sampling of rate up to 56 GS/s in 65-nm CMOS is presented in [2]. In [3] four 8-bit DACs with a conversion rate of 55~65 GS/s in 40-nm CMOS integrated on a SoC are reported. Another 6-bit RZ DAC with up to 50-GHz sampling clock and 4 Vpp differential output swing in 130-nm SiGe BiCMOS is presented in [4]. As the technology nodes scale down, DACs with even higher conversion rates become feasible for next generation optical transceivers with bit rates from 400 Gb/s to 1 Tb/s.