Dynamic partial reconfiguration manager

Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.

I. Introduction

S RAM-BASED FPGAs (in this work, shortened to only FPGAs) are widely used in streaming applications such as image and video processing because of their availability and versatility of resources providing high throughput data processing. Xilinx's Virtex FPGAs offer the capability of reconfiguring just some part of their resources even during the normal operation of the application. This process is known as partial reconfiguration [1] or dynamic partial reconfiguration (DPR) when it is done at run-time. This technique is currently used by multimedia, avionic, fault tolerant applications and other intelligent systems [2] [3] [4] [5] with limited resources requiring upgrade or security features. DPR can change the FPGA functionality by loading partial bitstreams, typically stored in flash memory, through any available configuration port, i.e. Slave SelectMAP, Slave Serial, JTAG, or Internal Configuration Access Port (ICAP, an internal representation of the SelectMAP interface) [6]. In order to perform DPR, Xilinx's proposed flow is handled by an embedded processor (MicroBlaze, ARM or PowerPC) that uses the OPB-HWICAP, [7] XPS-HWICAP [8] or AXI-HWICAP cores to control the ICAP. All cores require buffers and ICAP control capabilities and an external memory is usually required when big or several bitstreams are needed; consequently an additional memory controller must be used to retrieve data from the device, before sending it to the HWICAP. Such process spends several clock cycles that prevent the microprocessor from performing other tasks. Moreover, HWICAP can only be used with the MicroBlaze, PowerPC or ARM processors.