I. INTRODUCTION
The demand for mobile electronic devices of low-power and high-speed is driving designers to design for smaller silicon area, high speed, longer battery life and more reliability. Power dissipation is the limiting factor for hand held devices. as energy-efficiency is one of the most required features for high-performance and/or portable applications. The power-delay product (PDP) metric relates the amount of energy spent during the realization of a determined task, and stands as the more fair performance metric. Fast arithmetic computation cells inclusive of adders and multipliers are the most widely used circuits in VLSI systems. Digital signal processors rely on the efficient implementation of generic arithmetic logic units and floating point units to execute dedicated algorithms such as convolution and filtering [6], [10], [15], [16]. In most of these applications, multipliers have been the critical component and adder cells are in the critical paths of these complex arithmetic modules. Therefore design of ultra low power circuits becomes critical for portable applications. Thus, the design of a full-adder having low-power consumption and low propagation delay results of great interest for the implementation of modern digital systems. For ultra low power applications like implants and wireless sensor nodes, the most important design goal is to optimize for low power consumption. Digital hearing aids frequently employ the concept of filter banks whose complexity of computation requires more number of multiplications of higher power consumption. Therefore the construction of filter bank in Digital hearing aid with minimum number of multiplications is a desired design option. Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids for low power operation. [1], [2], [3].