ASIC Implementation of Time-Domain Digital Back Propagation for Coherent Receivers

Digital back propagation (DBP) is often proposed and implemented offline for the mitigation of nonlinear impairments in long-haul fiber communications. However, complexity in terms of chip area and power consumption in a realistic application-specific integrated circuit implementation is yet to be determined. Here, we implement time-domain DBP (TD-DBP) in a 28-nm fully-depleted silicon-on-insulator process technology, considering digital implementation aspects such as limited-resolution arithmetic and finite-length filters. We choose as example a coherent optical transmission system, viz. a single-channel, single-polarization, and 20-GBd 16-QAM system, for which the DBP is known to perform well. For the considered system, we find that the TD-DBP can enable a reach increase from 3400 to 5300 km, at a power dissipation of <;20 W (or, conversely, an energy dissipation of <;230 pJ/bit), at a pre-FEC BER of $10^{-2}$ .