Highly Efficient Chip-Scale Package LED Based on Surface Patterning

Chip-scale package (CSP) light-emitting diodes (LEDs) are considered as the next generation of highly efficient package LED. However, they suffer from total internal reflection that limits their light extraction efficiency (LEE). In this letter, surface patterning, in terms of microstructures, as a well-controlled surface roughness method is designed and applied on CSP-LED to improve the LEE. Based on simulation results, pyramid and flat top pyramid structures have been designed and optimized. Four types of layouts, including tightly, interlaced, distant and chessboard layout, are also compared. A LEE enhancement of more than 20% is achieved. Furthermore, the four layouts with pyramid structures are fabricated using nano-imprint technology. The experimental results match the simulated results well with only a mismatch of 2.9%. The fabricated layout shows an enhancement of 20.31% when pyramid structures are fully filling the surface. Surface patterned CSP-LED, therefore, exhibits a great potential for high efficient LED.