3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

Since the invention of radio, superheterodyne has been the architecture of choice for receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-band LO leakage and sensitivity to 2^nd-order intermodulation are simply avoided. Unfortunately, the high IF requires high-quality-factor (Q) band-pass filters for image rejection, which cannot be easily integrated in CMOS. This forced the CMOS receivers to migrate to zero (or low) IF and suffer from the abovementioned problems. Recently, there have been attempts to revisit the high IF operation by exploiting N-path filtering [1] and a combination of a discrete-time (DT) band-pass charge-sharing filtering with feedback filtering [2]. Here, we propose a superheterodyne RX architecture with full DT operation using only g_m stages, switches and capacitors. The transfer function is accurate and controlled by the clock frequency and precise capacitor ratios.

In DT zero-IF receivers, the signal is commonly sampled in quadrature at Nyquist rate , but then immediately decimated [3], [4]. While this decimation might be acceptable in narrowband ZIF RX, it creates images without enough attenuation in a high-IF receiver. In the proposed receiver structure, the input signal is sampled at directly at RF, giving an OSR of more than 2. This ensures no signal aliasing up to more than . This very high sampling rate is kept throughout the IF stage to create enough attenuation of unwanted frequencies before any decimation. The passive sampling mixer shown in Fig. 3.8.1 does both sampling of the signal and DT quadrature mixing. On each of the phases 1–4, the signal is sampled and then mixed with [1 0–1 0] and [0 1 0–1] in I and Q branches, respectively. The point of keeping the sampling rate is that all the data at the output of each mixer, including 0's data, should be read out and processed by the next stage. This avoids any early decimation. Output data of this mixer are DT charge packets stored on capacitors of subsequent stages. Figure 3.8.1: Fully DT superheterodyne receiver chain, including: 4x sampling mixer, DT complex BPF, and BB signal processing