A power efficient carry save adder and modified carry save adder using CMOS technology

Adders form an almost obligatory component of every contemporary integrated circuit. The primary requirement of the adder is that it is fast and efficient in terms of power consumption and chip area. In this paper we design a CMOS Logic based Carry Save adder and Modified carry save adder and to deliver with 250 nm, 65nm technology with low power by replacing the architecture for minimal power utilization.