VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder

A multiplier is one of the important hardware blocks in most digital and high performance systems such as microprocessors, FIR filter and digital signal processors etc. With improving in technology, many researchers have tried and are trying to design multipliers which offer high speed, low power consumption and less area. However area and speed are two most important constraints. So improving speed results always in larger area. So here we try to find out the best solution among the both of them. In order to reduce the hardware which ultimately reduces an area and power, Energy Efficient full adders plays an important role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM). A Reduced Complexity Wallace multiplier presented in this paper is having the same delay as that of Standard Wallace multipliers. In both multipliers, at the last stage Carry Propagating Adder (CPA) is used. This paper proposes use of Energy Efficient CMOS full adder in reduced complexity Wallace Multiplier at the place of Full adder of standard Wallace Multiplier in order to reduce Area, Power and improvement in speed. The Reduced complexity reduction method smartly reduces the number of half adders with 70-80% reduction in an area of half adders than standard Wallace multipliers.

I. Introduction

Multipliers are one the most important component of many systems. In high speed digital signal processing (DSP) and image processing multiplier play an vital role. In image processing fast Fourier transform (FFT) is one of the most important transform often used. A computational process of fast Fourier transform requires large number of multiplication and addition operation. The execution of these algorithms requires dedicated MAC and Arithmetic and Logic Unit (ALU) architectures. Multipliers and adders are the key element of these arithmetic units [8] as they lie in the critical path. With the recent advances in technology, many researchers have tried to implement increasingly efficient multiplier. They aim at offering low power consumption, high speed and reduced delay. One such multiplier is Standard Wallace Multiplier (SWM) [3]. SWM is fully parallel version of the multiplier, the carry save adders used in SWM are conventional full adders whose carries are not connected, so that three inputs are taken and two words are out. SWM also uses half adders in reduction phase. Reduced complexity Wallace multiplier (RCWM) [1] reduced number of half adders used in SWM with a slight increase in full adders to reduce the number of gates. Both the multipliers SWM and RCWM have same number of stages and delay is also same. This paper proposes use of Energy Efficient CMOS full adder in reduced complexity Wallace multiplier at the place of carry propagating adder in order to reduce power and improvement in speed.