Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations

Reducing supply voltage (V
_dd
) while keeping leakage current low is critical for minimizing energy consumption and improving mobile device battery life. The thermal limit of MOSFET subthreshold slope (SS) restricts lowering threshold voltage (V
_t
), causing significant performance degradation at low V
_dd
. A Tunneling Field Effect Transistor (TFET) is not limited by this thermal tail and may perform better at low V
_dd
[1,2]. In this paper, a leading N-TFET option - GaSb/InAs heterojunction - is atomistically modeled [3,4] and circuit simulation models are developed to predict 64% average energy savings against Si CMOS at Lg=13nm for a nanowire. Energy savings diminish to 21% without a good P-TFET option. Both MOSFET and TFET device variations are dominated by work-function variation, and TFET energy savings are slightly reduced when variations are considered.