I Introduction
Over the past decade, stress engineering has proved to be critical in improving the Si-CMOS device performance every successive technology node. More recently, integration of high-mobility III-V channel materials has been touted as a possible route for extending the life of Moore's law beyond Si-CMOS [1], [2]. Although III-V devices promise high per-formance, such solutions are riddled with formidable integration challenges, potentially higher costs and difficulties in high-volume manufacturing.