Design options for hetero-junction tunnel FETs with high on current and steep sub-threshold voltage slope

This work presents a systematic design study of nanowire Tunnel-FETs at L
_G
=17nm employing a 3D Poisson-NEGF solver based on a 8×8 k·p Hamiltonian and including phonon scattering. In particular: (a) we revisit the design of GaSb-InAs based hetero-junction tunnel-FETs showing that this system is unlikely to yield a broken bangap profile at the very narrow features necessary for a good sub-V
_T
slope value; (b) we propose new design options for hetero-junction tunnel-FETs, relying on the use of strain and of a graded molar fraction (x
_M
) in Al
_xM
Ga
_(1-xM)
Sb, which improve remarkably on current preserving optimal sub-V
_T
slopes; (c) we show that interface defects can frustrate any design strategy aiming at sub-V
_T
slope values below 60mV/dec.