Advanced Systems-on-Chip (SoC) designers use a variety of IP blocks including analog/mixed-signal IP, digital logic blocks, memory and interface IP. As designs continue to increase in size and use of more IP becomes essential, it is difficult to complete testing of large SoCs within the desired schedule and cost using traditional full-chip methodologies. At the same time test interfaces in these blocks may differ, making it extremely challenging and time-consuming to integrate and test all of the IP at the SoC level. Automation of IP test integration in the SoC and re-use of IP-level test patterns at the SoC level allows cutting weeks off the design and the design-for-test cycles and getting products to market quickly. Any such solution should also support the upcoming standards for accessing embedded SoC DFT structures, aiming to meet user requirements to the board-level test.
Abstract:
With technologies shrinking and design complexity increasing, it becomes crucial that embedded in chip test and repair solutions keep up with the advances in order to con...Show MoreMetadata
Abstract:
With technologies shrinking and design complexity increasing, it becomes crucial that embedded in chip test and repair solutions keep up with the advances in order to consistently provide superior chip quality and yield optimization. The embedded test approaches developed for designs done a few years ago are not sufficient for today's designs, which are bigger, faster, hierarchical and much more sensitive to area, timing and power. Similarly, the embedded test solutions developed e.g. for 28-nm technology nodes will not deliver the same level of test quality, diagnosis accuracy and repair efficiency for 14-nm technology nodes, as defects and failure mechanisms change with process technologies shrink.
Published in: Ninth International Conference on Computer Science and Information Technologies Revised Selected Papers
Date of Conference: 23-27 September 2013
Date Added to IEEE Xplore: 16 January 2014
ISBN Information: