A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters

A high-voltage high-speed gate driver to enable synchronous rectifiers with zero-voltage-switching (ZVS) operation is presented in this paper. A capacitive-coupled level-shifter (CCLS) is developed to achieve negligible propagation delay and static current consumption. With only 1 off-chip capacitor, the proposed gate driver possesses strong driving capability and requires no external floating supply for the high-side driving. A dynamic timing control is also proposed not only to enable ZVS operation in the converter for minimizing the capacitive switching loss, but also to eliminate the converter short-circuit power loss. Implemented in a 0.5μm HV CMOS process, the proposed CCLS of the gate driver can shift up a 5V signal to the 100V DC rail with sub-nanosecond delay, improving the FoM by at least 29 times compared with that of state-of-the-art counterparts. The dynamic dead-time control properly enables ZVS operation in a synchronous buck converter under different input voltages (30V to 100V). The power losses of the high-voltage buck converter are thus greatly reduced under different load currents, achieving a maximum power efficiency improvement of 11.5%.