Assessing reliability of nano-scaled CMOS technologies one defect at a time

In the deeply downscaled CMOS technologies with ~10 nm gate lengths only a handful of defects will be present in each device, while their relative impact on the device characteristics will be significant. The behavior of these defects is stochastic, voltage and temperature dependent, and widely distributed in time, resulting in each device behaving very differently during operation (Fig. 1) [1,2].