A Novel Foundry Yield Model Using Critical Area Analysis

A novel foundry yield model for integrated circuit products has been developed based on critical area scaling. The newly proposed model does not need the information of the defect density by failure mode. This has considerably simplified the model inputs, and avoided the complicated and costly process to obtain the accurate defect density by failure mode. First, the critical area concept and the existing methodology of yield projections are reviewed. Next, a novel product yield model is given based on the critical area scaling. The model tolerance of critical area variations is also discussed. Finally, actual yield data of 14 nm products is compared to the proposed model and the physical area based model. The proposed model has shown significantly improved accuracy to actual silicon data than a physical area based model across a range of products with different design styles and applications. The proposed model is also manufacturing friendly and can be easily adopted by a semiconductor company. The proposed model is not only critical for foundries which have high product mix from different customers, but also beneficial for fabless companies in yield forecast and financial planning.