On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator

Process variability is one of the major concerns in semiconductor manufacturing in advanced technology nodes. This paper explains an all-digital technique to estimate the impact of threshold voltage (V
_th
) of NMOS device under test (NDUT) using a reconfigurable ring oscillator (RRO) which consists of a chain of threshold voltage measurement cell (TVMC). The difference of periods of RRO due to two voltage levels, i.e., V
_dd
and (V
_dd
- V
_th
) at the intermediate node provides information about the impact of threshold voltage of an NDUT. A lognormal model is developed to extract the threshold voltage information from the RRO period difference. The maximum difference in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 1.5%. Measured results from 26 test chips in 130-nm process show the feasibility of estimating the V
_th
variability from the proposed RRO test structure. The proposed test circuit with 300 samples of NDUT occupies a silicon area of 280 × 64 μm
²
.