The Effect of Si Surface Flattening Process on the MISFET With High-k HfNx Multilayer Gate Dielectrics

Metal-insulator-semiconductor field-effect transistors (MISFETs) with high-k HfN
_x
multilayer gate dielectrics fabricated with Si surface flattening process were investigated. The Si surface flattening process was carried out by Ar/1.0%H
₂
annealing for 30 min. A higher I
_on
/ I
_off
current ratio was obtained by increasing the number of HfN
_x
gate dielectric layers while its characteristics such as drain current, saturation mobility and subthreshold swing (SS) are not markedly degraded. This is attributed to the thicker gate dielectrics. Furthermore, it is found that these characteristics are found to be effectively improved by Si surface flattening process.